South Korea and Japan Unveil Vertical HBM Architecture Designs to Boost AI Memory Bandwidth by 80%

At the 2026 IEEE/JSAP VLSI conference, research teams from South Korea's UNIST and Japan's University of Tokyo independently announced two new high-bandwidth memory (HBM) architectures—V-Die and MOSAIC—that rotate DRAM chips from a horizontal to vertical orientation to improve thermal dissipation and address AI chip memory bottlenecks.

UNIST's V-Die architecture rotates DRAM chips 90 degrees and positions them vertically using through-silicon vias (TSV), freeing up space for additional memory cells while introducing liquid cooling channels between chips. Simulation data shows V-Die achieves 540 tokens per second when running GPT-3 level workloads, nearly double the 296 tokens per second of conventional HBM4. Tokyo University's MOSAIC uses orthogonal chip stacking with contactless inter-chip interfaces using micro-inductor coupling, reaching 4 Gbps per channel and potentially doubling HBM4 capacity in DRAM-on-GPU configurations. Both designs aim to resolve the critical memory bandwidth bottleneck constraining current AI accelerators, though both remain at the academic simulation stage.