NVIDIA has decided to temporarily abandon TSMC’s COUPE (Compact Universal Photonic Engine) co-packaged optics solution and instead switch to Tower Semiconductor’s silicon photonics platform. According to engineering analysis from Irrational Analysis, the main reasons NVIDIA launched Plan B were delays in the development of TSMC’s titanium nitride (TiN) PDK and the fact that the development of 2D grating couplers did not meet expectations.
Plan A Exit: TSMC COUPE Faces SiN PDK Delays and 2D Grating Coupler Failures
According to engineering analysis from Irrational Analysis, the two major critical technical bottlenecks facing TSMC’s COUPE platform are as follows:
Titanium nitride (SiN) PDK development delays: TSMC’s silicon photonics process design kit (PDK) rollout has been delayed, directly affecting downstream customer circuit design timelines. The delay in the SiN PDK has not only impacted NVIDIA—multiple AI chip design companies are also evaluating TSMC’s silicon photonics process, and downstream design schedules have been pushed back in parallel.
2D grating coupler failures: Development of high-density 2D grating couplers failed to meet specifications, directly affecting the coupling efficiency of optical signals, which caused the COUPE program to fall behind schedule.
TSMC’s COUPE platform is its universal photonic engine platform, aiming to standardize and make optical components as interchangeable as transistors. CPO technology packages laser sources directly next to the switching chip, which can greatly shorten optical signal transmission distances and reduce power consumption and signal loss.
Plan B Takes the Lead: Tower Semiconductor’s NPO Architecture Technical Specifications and Performance Trade-offs
According to Irrational Analysis, Tower Semiconductor’s NPO architecture technical specifications are as follows: 200G/400G PAM4 modulation (replacing the original 50-64G NRZ); 16-wavelength DWDM (doubling the 8 wavelengths of Plan A to offset the problem of lower NPO bandwidth efficiency); a stronger equalizer (EQ) and driver (because the NPO electrical paths are longer and reflect more, bump capacitance is a key factor).
However, the Tower solution also has two costs: lower channel density (requiring more wavelengths to achieve the same bandwidth) and worse power efficiency (the power and noise requirements for grating lasers rise exponentially, raising SNR requirements and increasing the laser burden).
Common Questions
Why did NVIDIA abandon the TSMC COUPE solution and switch to Tower Semiconductor?
Based on engineering analysis from Irrational Analysis, the main reasons are two technical bottlenecks: delays in TSMC’s titanium nitride (SiN) PDK development and the 2D grating coupler development not meeting specifications. These issues directly affect the timeline of NVIDIA’s next-generation network architecture, forcing NVIDIA to activate an alternative solution (Plan B) and switch to Tower Semiconductor’s NPO architecture.
What is Tower Semiconductor’s silicon photonics technology background?
According to reports, Tower Semiconductor is the semiconductor foundry under Infineon, and its silicon photonics technology stems from years of photonic-electronic integrated circuit R&D in Germany, with particularly mature mass-production experience in datacom and telecom. NVIDIA’s shift to Tower indicates that silicon photonics development is not monopolized by TSMC alone.
What broader impact does the TSMC COUPE SiN PDK delay have on the industry?
According to reports, the TSMC COUPE platform is not only used by NVIDIA—multiple AI chip design companies are also evaluating TSMC’s silicon photonics process. Delays in the SiN PDK mean downstream design timelines are pushed back in sync, expanding the impact beyond NVIDIA alone. The specific development progress is subject to TSMC’s official announcements.
